Product Summary

The HY57V161610FTP is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. The HY57V161610FTP is organized as 2banks of 524,288x16. The HY57V161610FTP is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Parametrics

HY57V161610FTP absolute maximum ratings: (1)Ambient Temperature, TA: 0 to 70℃; -40 to 85℃; (2)Storage Temperature, TSTG: -55 to 125℃; (3)Voltage on Any Pin relative to VSS, VIN, VOUT: -1.0 to 4.6 V; (4)Voltage on VDD supply relative to VSS, VDD, VDDQ: -1.0 to 4.6 V; (5)Short Circuit Output Current, IOS: 50 mA; (6)Power Dissipation, PD: 1W; (7)Soldering Temperature, TSOLDER: 260℃.

Features

HY57V161610FTP features: (1)Voltage: VDD, VDDQ 3.3V supply voltage; (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch (Lead or Lead Free Package); (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM, LDQM; (6)Internal two banks operation; (7)Auto refresh and self refresh; (8)4096 Refresh cycles / 64ms ; (9)Programmable Burst Length and Burst Type: - 1, 2, 4, 8 or full page for Sequential Burst; - 1, 2, 4 or 8 for Interleave Burst; (10)Programmable CAS Latency; 1, 2, 3 Clocks; (11)Burst Read Single Write operation.

Diagrams

HY57V161610FTP functional block diagram

HY57V121620(L)T
HY57V121620(L)T

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Data Sheet

Negotiable 
HY57V161610D
HY57V161610D

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Data Sheet

Negotiable 
HY57V161610D-I
HY57V161610D-I

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Data Sheet

Negotiable 
HY57V161610E
HY57V161610E

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Data Sheet

Negotiable 
HY57V161610ET-I
HY57V161610ET-I

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Data Sheet

Negotiable 
HY57V161610ETP-I
HY57V161610ETP-I

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Data Sheet

Negotiable